This standard establishes the Universal Verification Methodology (UVM), a set of application programming interfaces (APIs) that defines a base class library (BCL) definition used to develop modular, scalable, and reusable components for functional verification environments. The APIs and BCL are based on the IEEE standard for SystemVerilog, IEEE Std 1800™.
IEC 62530-2 Ed. 2.0 en:2023
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SystemVerilog – Part 2: Universal Verification Methodology Language Reference Manual
International Electrotechnical Commission , 10/01/2023
Pages: 464
